1. Field of the Invention
This invention relates to a fault diagnosis apparatus for an LSI, and more particularly to a fault diagnosis apparatus useful for a disconnection fault of a wiring pattern and a recording medium on which a fault diagnosis program is recorded.
2. Description of the Related Art
As a technique useful for a fault diagnosis of an LSI, a method is available which employs an apparatus which can directly observe a signal behavior in the inside of an LSI (an apparatus of the type mentioned is hereinafter referred to an internal signal observation apparatus) such as electron beam tester (EB tester). However, since an internal signal observation apparatus of the type described requires much time for measurement, it is not effective for a large scale circuit to use only the internal signal observation apparatus from the beginning to trace or search for a fault site from an output with which an error has been observed since a very long time is required for observation of signals and narrowing down of fault site candidates.
Thus, several fault diagnosis techniques have been proposed wherein fault sites in an LSI are estimated from a result of comparison between output signals and scan-out signals of the LSI obtained from an LSI tester and expected values for them and places to be observed directly are reduced by a large number by means of an internal signal observation apparatus such as an EB tester.
For example, Japanese Patent Laid-Open Application No. Heisei 1-244384 discloses a technique wherein a circuit pattern in which only one route is activated from an input to an output of the circuit is used to perform a test and a fault site is estimated from failed outputs and passed outputs by comparison with expected values obtained by an LSI tester and a list of faults which are activated with the pattern then (hereinafter referred to as first prior art).
Japanese Patent Laid-Open Application No. Heisei 4-55776 discloses another technique which compares, making use of a fact that a designer can estimate a gate or a state which makes a cause of a fault from a result of a test by an LSI tester, a result of a simulation performed by assuming suspected fault sites and a result of comparison with expected values by an LSI tester to verify whether or not the estimation is correct (hereinafter referred to as second prior art).
Among various faults of LSI circuits, a disconnection of a wiring pattern and a disconnection by an incomplete contact exhibit high frequencies of occurrence. For example, a disconnection of a wiring line pattern upon production of an LSI which is caused by dust on a mask, a disconnection which arises from flowing of overcurrent during operation and a disconnection which is caused by deterioration by use for a long period of time are possible. Most wiring patterns have branches, and if a disconnection occurs intermediately of a branch, then a signal operates normally at a portion of the branch forwardly of the disconnected site while the signal does not operate in the branch rearwardly of the disconnected site but is fixed, entering a fault mode which cannot be represented by a single stuck-at fault.
The first prior art described above has a problem in that, since it presumes a single stuck-at fault as a fault, for such a disconnection fault of a wiring pattern which is a fault mode which cannot be represented by a single stuck-at fault as described above, it cannot effectively narrow down fault site candidates.
On the other hand, the second prior art can handle any fault and can diagnose also a disconnection fault intermediate of a branch of a wiring line. However, as an increase in scale and complication of a circuit proceeds, an increasing number of designers participate in cooperative development of an LSI, resulting in such a situation that almost none of the designers possibly knows the entire circuitry of the LSI to such a degree that a possible fault site can be estimated. Accordingly, the second prior art which presumes that a possible fault can be estimated by a designer cannot be applied well to an LSI of a large scale. Further, even if the second prior art is applied, if a designer estimates fault sites and confirms them one after another by a simulation, then very much labor is required, and therefore, this is not practical.